The present invention relates to a random access memory circuit, and more specifically to a magnetic random access memory circuit (called a xe2x80x9cMRAM circuitxe2x80x9d in this specification).
A magnetic random access memory includes a plurality of memory cells located at intersections of word lines and bit lines, each memory cell being basically constituted of a pair of ferromagnetic layers separated by an insulating or non-magnetic metal layer. Digital information is represented by the direction of magnetic vectors in the ferromagnetic layers, and is infinitely maintained unless it is intentionally rewritten. In order to write or change the state of the memory cell, a composite magnetic field which is generated by use of a word current and a bit current and which is larger than a threshold, is applied to the memory cell, so as to reverse the magnetization of the ferromagnetic layers.
U.S. Pat. No. 5,748,519 and IEEE Transaction On Components Packaging and Manufacturing Technologyxe2x80x94Part A, Vol. 170, No. 3, pp373-379 (the content of which are incorporated by reference in its entirety into this application) disclose a first example of the magnetic random access memory which includes a number of memory cells configured to utilize a giant magneto-resistive (GMR) effect. Referring to FIG. 1, there is shown a layout diagram of a simplified MRAM circuit including each memory cell configured to utilize the GMR effect. The MRAM circuit is conventionally formed on a semiconductor substrate on which other circuits are formed, so that the MRAM circuit and other circuits are formed on the same substrate in a mixed condition. As shown in FIG. 1, the MRAM circuit includes a memory array divided into a first array portion 604 and a second array portion 605, a decoder consisting of a row decoder 602 and a column decoder 603, and a comparator 606. The row decoder 602 and the column decoder 603 are connected to an address bus 601, respectively. In a reading operation, one of the first array portion 604 and the second array portion 605 is used as a reference cell. In each array portion, a plurality of GMR elements are connected in series in each one row. In the reading operation, a current is caused to flow in a selected row of each of the first array portion 604 and the second array portion 605, a difference between respective voltages generated in the first array portion 604 and the second array portion 605 is detected by the comparator.
U.S. Pat. No. 5,640,343 (the content of which is incorporated by reference in its entirety into this application) discloses a second example of the magnetic random access memory includes a number of memory cells configured to utilize a magnetic tunnel junction (MTJ) effect. Referring to FIG. 2, there is shown a MRAM circuit including each memory cell configured to utilize the MTJ effect. The shown MRAM circuit includes row decoders 701 and 702, column decoders 703 and 704, and a matrix circuit having a number of MTJ elements 711 to 715 and so on located at intersections of word lines 705, 706 and 707 extending between the row decoders 701 and 702 and bit lines 708, 709 and 710 extending between the column decoders 703 and 704. In this MRAM circuit, a stored information is distinguished dependent upon whether a sense current is large or small. However, this patent does not disclose a method for detecting the magnitude (large or small) of the sense current, nor does it show how to connect a comparator (sense amplifier).
In this first prior art example, a resistance of serially connected memory cells is directly detected. However, the resistance detected includes an on-resistance of a transistor connected in series with the row. In addition, a memory cell array and a reference cell array are separated or put apart from each other. Therefore, a reference signal is inclined to contain a parasite component, with the result that it is difficult to have a sufficient margin in operation. Accordingly, a high level of equality in characteristics is required for memory cells on the same wafer. In addition, since it is so configured to detect the voltage of a plurality of serially connected memory cells, a magnetically changed component of the resistance is small in comparison with the resistance of the whole of the row, with the result that a device variation and a noise resisting property are deteriorated. Furthermore, in order to make the detecting sensitivity large, it is necessary to enlarge a detecting current or to bring the GMR element into an elongated form so as to increase the device resistance This results in an increased power consumption and in an increased circuit area.
In the second prior art example, each memory cell includes a diode. Similarly, each memory cell can be easily constructed to include a transistor. In the memory cell including the diode or the transistor, however, the cell construction becomes complicated, and therefore, is difficult to integrate the circuit. On the other hand, it is not so easy to construct a two-dimensional array with only the magneto-resistive elements which cannot operate as a complete on-off switch, because a detouring of the current in the cells must be considered.
Furthermore, in conventional GMR elements, since the current is caused to flow in parallel to a film surface, a fundamental resistance is equivalent to a wiring resistance. Accordingly, if a wiring conductor, a transistor and a magneto-resistive element are connected in series and the voltage of the whole of the series-connected circuit is directly measured, a voltage drop occurring across the wiring conductor and the transistor is not negligible, and a highly precise reading circuit (sense amplifier) becomes necessary.
Journal of Magnetics Society of Japan, Vol. 23, No. 1-2, pp55-57 mentions that a tunnel magneto-resistive element (TMR element) has such a feature that when a voltage applied between opposite ends of the junction increases, the magneto-resistive ratio (MR ratio) decreases. This is generally called a bias effect and is well known to persons skilled in the art. Because of this bias effect, even if a large voltage is applied across the TMR element, the changed component of the device voltage caused by a magnetic field does not necessarily proportionally become large. Therefore, a highly precise reading circuit becomes necessary.
Journal of Magnetism and Magnetic Materials, Vol. 198-199, No. 1-2, pp164-166 mentions that a large voltage is applied between opposite ends of the TMR element having a thin tunnel barrier, there is a problem in which a tunnel barrier is broken by an electric field and heat, so that a device lift is shortened.
Accordingly, it is an object of the present invention to provide an MRAM circuit having a large operation margin, by eliminating influence of variation in characteristics of magneto-resistive elements depending upon a geographical location on the same wafer, to the utmost.
Another object of the present invention is to provide a highly sensitive MRAM circuit capable of reading at a high speed, by preventing a lowering of the detecting sensitivity of a reading circuit, attributable to a voltage drop caused by the resistance of the wiring conductor and the transistor connected in series with the magneto-resistive element.
Still another object of the present invention is to provide an MRAM circuit having a tunnel type magneto-resistive element, which is a highly sensitive and can be read at a high speed, by preventing the bias effect of the magneto-resistance and the breakage of the tunnel barrier.
A further object of the present invention is to provide an MRAM circuit which can be integrated with a high integration density, by eliminating the diode or the transistor in the basic memory cell.
The above and other objects of the present invention are achieved in accordance with the present invention by a magnetic random access memory circuit comprising:
a memory cell array having a plurality of sense lines, a plurality of word lines intersecting the plurality of sense lines, a number of magneto-resistive elements located at intersections between the plurality of sense lines and the plurality of word lines, each of the magneto-resistive elements being connected between one sense line and one word line;
a plurality of capacitors of the number corresponding to the number of the plurality of sense lines, the plurality of capacitors being previously charged to a high voltage before a reading operation is carried out, each of the plurality of capacitors being connected to a corresponding sense line of the plurality of sense lines through a voltage drop means so that a voltage lower than the high voltage charged in the capacitors is applied to the plurality of sense lines; and
means for equalizing the potential of all the plurality of sense lines and all not-selected word lines of the plurality of word lines and for grounding a selected word line of the plurality of word lines so that an electric charge previously stored in the capacitor connected through the voltage drop means to a selected sense line is discharged through the voltage drop means, the selected sense line, a selected magneto-resistive element, and the selected word line, whereby information stored in the selected magneto-resistive element is read out by a potential on the capacitor.
According to another aspect of the present invention, there is provided a magnetic random access memory circuit comprising:
a memory cell array having a plurality of sense lines, a plurality of word lines intersecting the plurality of sense lines, a number of magneto-resistive elements located at intersections between the plurality of sense lines and the plurality of word lines, each of the magneto-resistive elements being connected between one sense line and one word line;
an X peripheral circuit connected to the plurality of word lines and including an X decoder receiving an X address portion of a given address;
a Y peripheral circuit connected to the plurality of sense lines and including a Y decoder receiving an Y address portion of the given address;
wherein the Y peripheral circuit includes a plurality of pairs of series-connected first and second MOS transistors connected to the plurality of sense lines, respectively, each first MOS transistor having one end connected to a corresponding sense line of the plurality of sense lines, the other end connected to one end of the corresponding second MOS transistor, a gate connected to a reference voltage circuit, each second MOS transistor having the other end connected to a voltage supply and a gate connected to receive a corresponding output of the Y decoder, a connection node between the first MOS transistor and the second MOS transistor being connected to one end of a capacitor having the other end connected to ground,
wherein the X peripheral circuit includes a plurality of pairs of series-connected third and fourth MOS transistors having their gate connected to receive a corresponding output of the X decoder so as to operate complementarily to each other, the third MOS transistor having one end connected to a voltage supply and the other end connected to one end of the fourth MOS transistor, the other end of the fourth MOS transistor being connected to ground, a connection node of the third and fourth MOS transistors being connected to a corresponding word line of the plurality of word lines.
In one embodiment of the magnetic random access memory circuit, the Y peripheral circuit includes a plurality of differential amplifiers, each of the differential amplifiers having a pair of inputs connected to a pair of the capacitors connected through a pair of the first MOS transistors to a pair of adjacent sense lines, so that one of a pair of magneto-resistive elements connected to the same word line and to the pair of adjacent sense lines constitutes a memory cell, and the other of the pair of magneto-resistive elements constitutes a reference cell which stores data complementary to data stored in the memory cell, whereby a difference between voltages of the pair of capacitors connected to the pair of adjacent sense lines through the pair of first MOS transistors, respectively, generated dependently upon respective resistance value conditions of the memory cell and the reference cell, is detected by the differential amplifier.
Another embodiment of the magnetic random access memory circuit can further includes:
a second X peripheral circuit provided in symmetry to the first mentioned X peripheral circuit with respect to the Y peripheral circuit, the second Y peripheral circuit having the same construction as that of the first mentioned X peripheral circuit; and
a second memory cell array provided in symmetry to the first mentioned memory cell array with respect to the Y peripheral circuit, the second memory cell array having the same construction as that of the first mentioned memory cell array;
the Y peripheral circuit being in common to the first mentioned memory cell array and the second memory cell array,
each of the first mentioned memory cell array and the second memory cell array including a plurality of reference resistors connected between at least one word line and the plurality of sense lines, respectively,
wherein when a magneto-resistive element included in one of the first mentioned memory cell array and the second memory cell array, is selected to be read out, the voltage of the capacitor connected to the selected magneto-resistive element through the first MOS transistor is compared with the voltage of the capacitor connected to one reference resistor through the first MOS transistor in the other of the first mentioned memory cell array and the second memory cell array.
Still another embodiment of the magnetic random access memory circuit can further includes a plurality of comparators each having one input connected to the reference voltage circuit, the other input connected to the corresponding sense line, and an output connected to the gate of the corresponding first MOS transistor so that the potential on the corresponding sense line is precisely feedback-controlled on the basis of a reference voltage of the reference voltage circuit.
According to still another aspect of the present invention, there is provided a magnetic random access memory circuit comprising:
a memory cell array having a plurality of sense lines, a plurality of word lines intersecting the plurality of sense lines, a number of magneto-resistive elements located at intersections between the plurality of sense lines and the plurality of word lines, each of the magneto-resistive elements being connected between one sense line and one word line;
an X peripheral circuit connected to the plurality of word lines and including an X decoder receiving an X address portion of a given address;
a Y peripheral circuit connected to the plurality of sense lines and including a Y decoder receiving an Y address portion of the given address;
wherein the Y peripheral circuit includes:
a plurality of pairs of parallel-connected first and second MOS transistors having their gate connected to receive corresponding outputs of the Y decoder, respectively, each of the pairs of first and second MOS transistors being provided for a corresponding one of the plurality of sense lines, one end of each of the first and second MOS transistors being connected to a voltage supply, the other end of the first and second MOS transistors being connected to ground through a first capacitor and a second capacitor, respectively;
a plurality of pairs of series-connected third and fourth MOS transistors having their gates connected to receive a corresponding output of the Y decoder so as to operate complementarily to each other, each pair of the pairs of series-connected third and fourth MOS transistors being connected between the other end of the corresponding first MOS transistor and the other end of the corresponding second MOS transistor; and
a plurality of fifth MOS transistors having their gates connected to a reference voltage circuit, each of the plurality of fifth MOS transistors having one end connected to a connection node between the corresponding seventh and eighth MOS transistors, and the other end connected to a corresponding sense line of the plurality of sense lines,
whereby a voltage on the connection node between the first capacitor and the corresponding first MOS transistor and a voltage on the connection node between the second capacitor and the corresponding second MOS transistor are compared for reading out data on a selected magneto-resistive element connected to the corresponding sense line,
wherein the X peripheral circuit includes a plurality of pairs of series-connected sixth and seventh MOS transistors having their gate connected to receive a corresponding output of the X decoder so as to operate complementarily to each other, the sixth MOS transistor having one end connected to a voltage supply and the other end connected to one end of the eleventh MOS transistor, the other end of the eleventh MOS transistor being connected to ground, a connection node of the tenth and eleventh MOS transistors being connected to a corresponding word line of the plurality of word lines,
wherein the magnetic random access memory circuit further includes a timing controller for controlling respective operation timings of the X decoder and the Y decoder.
An embodiment of the magnetic random access memory circuit can further includes a plurality of comparators each having one input connected to the reference voltage circuit, the other input connected to the corresponding sense line, and an output connected to the gate of the corresponding fifth MOS transistor so that the potential on the corresponding sense line is precisely feedback-controlled on the basis of a reference voltage of the reference voltage circuit.
In the above mentioned magnetic random access memory circuits in accordance with the present invention, each of the magneto-resistive elements can be constituted of a tunnel magneto-resistive element or a giant magneto-resistive element.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.